Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit

ABSTRACT

A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application for patent Ser. No. 14/724,975 filed May 29, 2015, the disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD

The present invention relates to integrated circuits and, in particular, to the formation of metal-filled vias, trenches or contact openings in the metallization (M), premetallization dielectric (PMD) or interlevel dielectric (ILD) layers of an integrated circuit.

BACKGROUND

Reference is now made to FIG. 1 showing the general configuration of a conventional metal oxide semiconductor (MOS) field effect transistor (FET) 10 device. A substrate 12 supports the transistor. In this example, the substrate is of the silicon-on-insulator substrate 12 type which includes a substrate layer 14, a buried oxide (BOX) layer 16 and a semiconductor layer 18. An active region 20 for the transistor device is delimited by a peripherally surrounding shallow trench isolation 22 that penetrates through the layer 18. Within the active region 20, the layer 18 is divided into a channel region 30 which has been doped with a first conductivity type dopant, a source region 32 (adjacent the channel region 30 on one side) which has been doped with a second conductivity type dopant, and a drain region 34 (adjacent the channel region 30 on an opposite side from the source region 32) which has also been doped with the second conductivity type dopant. Where the MOSFET 10 device is of the p-channel type, the first conductivity type dopant is p-type and the second conductivity type is n-type. Conversely, where the MOSFET device is of the n-channel type, the first conductivity type dopant is n-type and the second conductivity type is p-type. A gate stack 36 is provided above the channel region 30. This gate stack 36 typically comprises a gate dielectric 38, a gate electrode 40 (for example, of metal and/or polysilicon material) and sidewall spacers 42 made of an insulating material such as silicon nitride (SiN) deposited on the sides of the gate dielectric 38 and gate electrode 40. An interlevel dielectric (ILD) or pre-metallization dielectric (PMD) layer 46 is provided above the substrate and the gate stack. A top surface 48 of the layer 46 is processed with a chemical-mechanical polishing (CMP) process to define a planar surface. A set of metal contacts 50, typically formed of tungsten, extend from the top surface 48 through the ILD/PMD layer 46 in metal-filled contact openings to make electrical contact with the source region 32, drain region 34 and gate electrode 40. A first metallization layer M1 is then provided above the ILD/PMD layer 46, with the first metallization layer M1 comprising metal lines 54 formed in metal-filled via and/or trench openings in contact with the contacts 50 and surrounded by a planarized dielectric material layer 56.

As feature sizes in integrated circuit devices continue to shrink and operational speed increases, there is a need to make a thicker ILD/PMD layer 46 so as to reduce capacitance between the first metallization layer M1 and the active region 20 as well as between the first metallization layer M1 and the gate electrode 40. The thicker ILD/PMD layer 46 and reduced feature size accordingly necessitates the use of high aspect ratio metal contacts 50 (i.e., contacts made in openings with a height/width ratio >>1, for example, ≧4). It is a challenge to provide such high aspect ratio contacts without incurring problems associated with open yield and increased contact resistance. There is accordingly a need in the art for an improved contact configuration for interconnecting the first metallization layer M1 to both the active region 20 and the gate electrode 40.

In addition, improved structures for the metal lines and metal vias in the metallization layers of integrated circuits are needed to ensure device reliability and improve signal performance through resistance adjustment.

SUMMARY

In an embodiment, an integrated circuit comprises: a substrate; and conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; wherein: the first interconnect structure is adjacent to the second interconnect structure; the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level; the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure; the second interconnect structure includes a first substructure at the first level and a second substructure at the second level; the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure; and the second substructure of the second interconnect structure having a length greater than a length of the second substructure of the first interconnect structure.

In an embodiment, an integrated circuit comprises: a substrate; and conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and wherein: the first interconnect structure is adjacent the second interconnect structure; the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level; the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure; the second interconnect structure includes a first substructure at the first level and a second substructure at the second level; the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; and wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.

In an embodiment, an integrated circuit comprises: a substrate; and conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and wherein: the first interconnect structure is adjacent to the second interconnect structure; the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level; the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure; the second interconnect structure includes a first substructure at the first level and a second substructure at the second level; the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure; the second substructure of the second interconnect structure having a length greater than a length of the second substructure of the first interconnect structure; and wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

FIG. 1 illustrates the configuration of a prior art MOSFET device; and

FIGS. 2A-2D illustrate the configuration of contacts in accordance with an embodiment implemented with an example of a MOSFET device;

FIG. 3 illustrates a perspective view of the gate electrode and the contacts for the configuration shown in FIGS. 2A-2D;

FIGS. 4A-4D illustrate the configuration of contacts in accordance with an embodiment implemented with an example of a MOSFET device;

FIG. 5 illustrates a perspective view of the gate electrode and the contacts for the configuration shown in FIGS. 4A-4D;

FIGS. 6-8 illustrates perspective views of alternative arrangements of the contacts; and

FIG. 9 illustrates the configuration of metal-filled vias and trenches for a metallization layer of an integrated circuit;

FIG. 10 illustrates a perspective view of certain structures shown in FIG. 9;

FIG. 11 illustrates a perspective view of an alternate structure.

The illustrations provided are not necessarily drawn to scale.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made to FIGS. 2A-2D which illustrate the configuration of contacts in accordance with an embodiment implemented with an example of a MOSFET device 110 as an integrated circuit. FIGS. 2A-2B are parallel cross-sectional views taken offset from each other in a direction into/out of the page. FIGS. 2C-2D are parallel cross-sectional views taken offset from each other in a direction into/out of the page, with the views of FIGS. 2C-2D being orthogonal to the views of FIGS. 2A-2B.

A substrate 112 supports the MOSFET device 110. In this example, the substrate is of the silicon-on-insulator substrate 112 type which includes a substrate layer 114, a buried oxide (BOX) layer 116 and a semiconductor layer 118 (although it will be understood that the features disclosed herein are equally applicable to integrated circuits fabrication with a bulk or other semiconductor substrate as support). An active region 120 for the transistor device is delimited by a peripherally surrounding shallow trench isolation 122 that penetrates through the layer 118. Within the active region 120, the layer 118 is divided into a channel region 130 which has been doped with a first conductivity type dopant, a source region 132 (adjacent the channel region 130 on one side) which has been doped with a second conductivity type dopant, and a drain region 134 (adjacent the channel region 130 on an opposite side from the source region 132) which has also been doped with the second conductivity type dopant. Where the MOSFET 110 device is of the p-channel type, the first conductivity type dopant is p-type and the second conductivity type is n-type. Conversely, where the MOSFET device is of the n-channel type, the first conductivity type dopant is n-type and the second conductivity type is p-type. A gate stack 136 is provided above the channel region 130. This gate stack 136 typically comprises a gate dielectric 138, a polysilicon material gate electrode 140 and sidewall spacers 142 made of an insulating material such as silicon nitride (SiN) deposited on the sides of the gate dielectric 138 and polysilicon material gate electrode 140. An interlevel dielectric (ILD) or pre-metallization dielectric (PMD) layer 146 is provided above the substrate and the gate stack. A top surface 148 of the layer 146 is processed with a chemical-mechanical polishing (CMP) process to define a planar surface.

The ILD/PMD layer 146 comprises a plurality of sub-layers including: a first sub-layer 146(1), a second sub-layer 146(2) and a third sub-layer 146(3). Although three sub-layers are shown, it will be understood that layer 146 may comprise more sub-layers than three if demanded by the application and the geometry of the device. The first sub-layer 146(1) has a thickness which is generally the same as a thickness of the gate stack 136. This is not a requirement, but in many instances the sub-layer 146(1) is deposited and chemically-mechanically polished (CMP) stopping at the top of the gate stack 136. This operation may be performed in connection with implementation of replacement gate processes as known in the art. The second and third sub-layers 146(2) and 146(3) may have thicknesses as desired, which may be thicker, thinner or generally equal to the thickness of the first sub-layer 146(1). These additional sub-layers beyond sub-layer 146(1) are provided to increase the thickness of the layer 146 to a desired thickness separating the substrate from back-end-of-line (BEOL) structures such as metallization layers.

A set of metal contacts 150, typically formed of tungsten, extend from the top surface 148 through the ILD/PMD layer 146 to make electrical contact with each of the source region 132 and drain region 134. A metal contact 152, typically formed of tungsten, extends from the top surface 148 through the ILD/PMD layer 146 to make electrical contact with the gate electrode 140.

With respect to the contacts (also referred to as interconnect structures) 150 for the source region 132 and drain region 134, a first sub-contact (or substructure) 150(1) is provided in the first sub-layer 146(1). The first sub-contact 150(1) has a thickness equal to the thickness of the first sub-layer 146(1). The first sub-contact 150(1) has a first width as shown in FIG. 2A and a first length as shown in FIG. 2C.

Additionally, a second sub-contact 150(2) is provided in the second sub-layer 146(2). The second sub-contact 150(2) has a thickness equal to the thickness of the second sub-layer 146(2). The second sub-contact 150(2) has a second width as shown in FIG. 2A and a second length as shown in FIG. 2C which is different from the first length. The second width may, for example, equal the first width and the second length may be less than the first length.

Additionally, a third sub-contact 150(3) is provided in the third sub-layer 146(3). The third sub-contact 150(3) has a thickness equal to the thickness of the third sub-layer 146(3). The third sub-contact 150(3) has a third width as shown in FIG. 2A and a third length as shown in FIG. 2C different from the first and second lengths. The third width may, for example, equal the first and second widths and the third length may be less than the second length.

The first, second and third sub-contacts 150(1)-150(3) are in series electrical connection with each other to define the contact 150 which extends from the top surface 148 through the ILD/PMD layer 146 to make physical and electrical contact with the source region 132 or drain region 134. It will be noted that the lengths of the sub-contacts 150 progressively decrease in size the further the sub-contact is from the planar surface 148.

With respect to the contact (also referred to as an interconnect structure) 152 for the gate electrode 140, a first sub-contact (or substructure) 152(1) is provided in the second sub-layer 146(2). The first sub-contact 152(1) has a thickness equal to the thickness of the second sub-layer 146(2). The first sub-contact 152(1) has a first width as shown in FIG. 2D and a first length as shown in FIG. 2B.

Additionally, a second sub-contact 152(2) is provided in the third sub-layer 146(3). The second sub-contact 152(2) has a thickness equal to the thickness of the third sub-layer 146(3). The second sub-contact 152(2) has a second width as shown in FIG. 2D and a second length as shown in FIG. 2B different from the first length. The second width may, for example, equal the first width and the second length may be greater than the first length.

The first and second sub-contacts 152(1)-152(2) are in series electrical connection with each other to define the contact 150 which extends from the top surface 148 through the ILD/PMD layer 146 to make physical and electrical contact with the gate electrode 140. It will be noted that the lengths of the sub-contacts 152 progressively increase in size the further the sub-contact is from the planar surface 148.

In an embodiment, a volume of conductive material for the contact 150 (to either the source region or drain region) is substantially equal to a volume of conductive material for the contact 152 (to the gate region). In this context, the volumes of conductive material are considered to be substantially equal if they are within 5% of each other. To accomplish this design goal, the layout designer selects the widths and lengths of the sub-contacts for each of the sub-layers.

A first metallization layer M1 is then provided at the top surface 148 of the ILD/PMD layer 146, with the first metallization layer M1 comprising metal lines 154 in contact with the contacts 150 and 152 and surrounded by a planarized dielectric material layer 156. Additional metallization layers (not shown) may be provided above the first metallization layer M1 in a manner well known in the art. The metallization layers may, for example, be formed using well known damascene processes. The metal lines 154 of the metallization layer M1 are configured to make physical and electrical contact to a plurality of contacts such as, for example, shown in FIG. 2C at reference 180 with metal line 154 making electrical connection through contacts to two different source regions 132. The illustration of source region contact is by example only as the metal lines of the metallization layer M1 may be provided to make contact to multiple drain regions, multiple gate regions or multiple combinations of source, drain and gate regions in accordance with the integrated circuit design.

FIG. 3 illustrates a perspective view of the gate electrode 140 and the contacts 150 and 152 for the configuration shown in FIGS. 2A-2D. The contacts 150 are shown in contact with and extending upwardly from the source region 132 and drain region 134 formed in the substrate 112 semiconductor layer 118. The contact 152 is shown in contact with and extending upwardly from the gate electrode 140 formed above the substrate 112 semiconductor layer 118.

In an embodiment utilizing a replacement metal gate technology, the gate electrode 140 may instead comprise a metal fill material 140′ as shown in FIGS. 4A-4D with FIG. 5 illustrating a perspective view of the gate electrode 140′ and the contacts 150 and 152. Like reference numbers refer to like or similar parts as described above.

In this configuration, with respect to the contacts 152 for the gate electrode, a first sub-contact 152(1) comprising the replacement metal gate 140′ is provided in the first sub-layer 146(1). The first sub-contact 150(1) has a thickness generally equal to the thickness of the first sub-layer 146(1) (taking into account other structures of the gate stack such as the gate dielectric and work function metal, for example). The first sub-contact 150(1) has a first width as shown in FIG. 4D and a first length as shown in FIG. 4B.

Additionally, a second sub-contact 152(2) is provided in the second sub-layer 146(2). The second sub-contact 152(2) has a thickness equal to the thickness of the second sub-layer 146(2). The second sub-contact 152(2) has a second width as shown in FIG. 4D and a second length as shown in FIG. 4B. It will be note in this implementation the length of the second sub-contact 152(2) extends perpendicular to the length of the first sub-contact 152(1). The length of the second sub-contact 152(2) is likely to be different from the length of the first sub-contact 152(1). The second width may, for example, equal the first width and the second length may be greater than or less than the first length depending on application.

Additionally, a third sub-contact 152(3) is provided in the third sub-layer 146(3). The third sub-contact 152(3) has a thickness equal to the thickness of the third sub-layer 146(3). The third sub-contact 152(3) has a third width as shown in FIG. 4D and a third length as shown in FIG. 4B which is different from the second length. The third width may, for example, equal the first and second widths and the third length may be greater than the second length.

Although the contacts 150 and 152 are shown in FIGS. 3 and 5 to extend in their lengths generally perpendicular to each other, it will be understood that this is not a requirement. FIG. 6 illustrates a perspective view of the contacts 150 and 152 in a configuration where the lengths of the contacts extend parallel to each other. FIG. 6 further shows contact 150 in contact with and extending upwardly from a first region 132′ formed in the substrate 112 semiconductor layer 118, and shows contact 152 in contact with and extending upwardly from a second region 134′ formed in the substrate 112 semiconductor layer 118. The regions 132′ and 134′ may, for example, comprise source and drain regions, respectively, of a transistor device. The regions 132′ and 134′ may alternatively comprise any substrate region in an integrated circuit device (for example, bipolar transmitter emitter region, bipolar transmitter base region, bipolar transmitter collector region, FinFET structure regions, or UTBB/ETSOI planar source, drain or gate regions). It will further be noted that the lengths of the sub-contacts are different with respect to each of the sub-contacts forming a contact. For one contact (for example, contact 150), the lengths increase moving away from the substrate doped region 132′, and for another contact (for example, contact 152), the lengths decrease moving away from the substrate doped region 134′. In an embodiment, as shown in FIG. 6, the sub-contacts on different sub-layers may be configured to overlap each other as indicated at reference 168 in a direction perpendicular to the surface of the substrate.

While rectangular prism structures are shown in FIGS. 3 and 5-6, it will be understood this is just an example of the shape which may be used for the contacts 150 and 152. FIG. 7 illustrates a perspective view of the contacts 150 and 152 utilizing a circular prism (cylindrical) shape. In this implementation, it will be noted that the lengths (specifically, the diameters) of the sub-contacts are different with respect to each of the sub-contacts forming a contact. For one contact (for example, contact 150), the lengths (diameters) decrease moving away from the substrate doped region 132′, and for another contact (for example, contact 152), the lengths (diameters) increase moving away from the substrate doped region 134′.

FIG. 8 shows contacts 150 and 152 in a perpendicular orientation like that shown in FIGS. 3 and 5. It will further be noted that the lengths of the sub-contacts are different with respect to each of the sub-contacts forming a contact. For one contact (for example, contact 150), the lengths increase moving away from the substrate doped region 132′, and for another contact (for example, contact 152), the lengths decrease moving away from the substrate doped region 134′. FIG. 8 further shows, at reference 168, a perpendicular overlap with respect to sub-contacts in different sub-layers.

It will be noted that a volume of conductive material in the first and second contacts of the implementations shown in FIGS. 6-8 is preferably substantially equal. In this context, the volumes of conductive material are considered to be substantially equal if they are within 5% of each other.

In an embodiment, the first sub-contact 150(1) and the first sub-contact 152(1) in any of the disclosed implementations may be made of a first metal material such as, for example, tungsten. The remaining sub-contacts, such as the second and third sub-contacts 150(2)-150(3) and second and third sub-contacts 152(2) and 152(3) may be made of the same first material or, in an alternative implementation, made of a second metal material such as, for example, copper. In this regard, the metal material used for the metal lines 154 of the metallization layer M1 may also comprise, for example, copper. This use of the first metal material (tungsten) is consistent with the use of tungsten material for contacts and replacement metal gate structures at the first sub-layer, while the use of the second material (copper) for the sub-contacts in the remaining sub-layers supports the known advantages of copper use for wiring lines in integrated circuit devices. Aluminum presents an alternative second material choice.

Each of the sub-contacts may further include a barrier liner (for example, made of titanium nitride (TiN)) to protect against diffusion of the metal species used for the sub-contact into the sub-layers of the ILD/PMD layer 146.

Conventional deposit, pattern and fill process steps may be used to produce the sub-layers and sub-contacts. For example, a mask defining the location of openings for the sub-contacts may be produced on top of a given sub-layer of the ILD/PMD layer 146. An opening is then formed in that given sub-layer using the mask and a reactive ion etch (ME) is performed through the mask. The etch should extend completely through the given sub-layer to form the opening. An atomic layer deposition (ALD) technique is then used to deposit the metal barrier liner (such as TiN) on the walls of the opening, and a metal filling process (such as thermal chemical vapor deposition (CVD)) is then used to fill the opening with the metal material of the sub-contact (such as tungsten or copper). A chemical-mechanical polishing (CMP) process is then performed to remove excess metal barrier and fill material, with the CMP stopping at the top of the given sub-layer of the ILD/PMD layer 146. A chemical vapor deposition (CVD) process is then performed to deposit the next sub-layer of the ILD/PMD layer 146. The previous steps are then repeated to form the sub-contact in that next sub-layer. The process may be repeated as many times as are necessary to define the thickness of the ILD/PMD layer 146 from multiple deposited, patterned and filled sub-layers with sub-contacts. For example, the ILD/PMD layer 146 may have a thickness of 120-140 nm, with each sub-layer having a thickness of between 30-100 nm. The minimum width of the sub-contacts is set by the minimum dimension of the lithographic process used for fabrication. Conventional back-end-of-line (BEOL) processes are then performed to provide the necessary metallization levels.

Although specific reference is made herein to a planar MOSFET device and the formation of contacts for source, drain and gate, it will be understood that the techniques and structures for contacts described herein are applicable to an integrated circuit device including, without limitation, bipolar transistor devices, FinFET devices, diode devices, planar transistor devices with source and drain regions formed from UTBB or ETSOI substrates, and the like.

The structures described above for use as contacts in the ILD/PMD layer 146 may be advantageously extended for use in metallization layers. Reference is accordingly made to FIG. 9 which illustrates the configuration of metal-filled vias and trenches for a metallization layer M1 of an integrated circuit. The metallization layer M1 includes a dielectric material layer 156 having a planar top surface 158 that is formed on the top surface 148 of the ILD/PMD layer 146. Metal lines 154(1) and 154(2), typically formed of copper or aluminum, are formed in the dielectric material layer 156 to extend from the top surface 158 to the top surface 148 in order to make physical and electrical connection to contacts 150 and/or 152.

FIG. 9 shows the structures in the substrate and the ILD/PMD layer 146 as presented in FIGS. 2A-2D, but it will be understood that the structures as shown in FIGS. 4A-4D are equally applicable.

The dielectric material layer 156 comprises a plurality of sub-layers including: a first sub-layer 156(1), a second sub-layer 156(2) and a third sub-layer 156(3). Although three sub-layers are shown, it will be understood that layer 156 may comprise more sub-layers than three if demanded by the application and the geometry of the device. The first, second and third sub-layers 156(1), 156(2) and 156(3) may have different or substantially same thicknesses as desired by the application and routing of wiring.

Although disclosed in the context of the M1 metallization layer, it will be understood that the sub-layers are equally applicable to any of the included further metallization layers (M2-Mn) required by the integrated circuit.

With respect to the metal line (also referred to as an interconnect structure) 154(1), a first sub-line (or substructure) 164(1) is provided in the first sub-layer 156(1). The first sub-line 164(1) has a thickness equal to the thickness of the first sub-layer 156(1). The first sub-line 164(1) has a first width and a first length.

Additionally, a second sub-line 164(2) is provided in the second sub-layer 156(2). The second sub-line 164(2) has a thickness equal to the thickness of the second sub-layer 156(2). The second sub-line 164(2) has a second width which is different from the first width and a second length. The second width may, for example, be less than the first width and the second length may be equal to the first length.

Additionally, a third sub-line 164(3) is provided in the third sub-layer 156(3). The third sub-line 164(3) has a thickness equal to the thickness of the third sub-layer 156(3). The third sub-line 164(3) has a third width different from the first and second widths and a third length. The third width may, for example, be less than the first and second widths and the third length may be equal to the second length.

The first, second and third sub-lines 164(1)-164(3) are in series electrical connection with each other to define the first line 154(1) which extends from the top surface 158 through the dielectric layer 156 to make physical and electrical contact with the contact 150 for the source region 132. It will be noted that the widths of the sub-lines 164 progressively decrease in size the further the sub-line is from the planar surface 148.

With respect to the metal line 154(2), a first sub-line 164(1) is provided in the first sub-layer 156(1). The first sub-line 164(1) has a thickness equal to the thickness of the first sub-layer 156(1). The first sub-line 164(1) has a first width and a first length.

Additionally, a second sub-line 164(2) is provided in the second sub-layer 156(2). The second sub-line 164(2) has a thickness equal to the thickness of the second sub-layer 156(2). The second sub-line 164(2) has a second width which is different from the first width and a second length. The second width may, for example, greater than the first width and the second length may be equal to the first length.

Additionally, a third sub-line 164(3) is provided in the third sub-layer 156(3). The third sub-line 164(3) has a thickness equal to the thickness of the third sub-layer 156(3). The third sub-line 164(3) has a third width different from the first and second widths and a third length. The third width may, for example, be greater than the first and second widths and the third length may be equal to the second length.

The first, second and third sub-lines 164(1)-164(3) are in series electrical connection with each other to define the second line 154(2) which extends from the top surface 158 through the dielectric layer 156 to make physical and electrical contact with the contact 150 for the drain region 134. It will be noted that the widths of the sub-lines 164 progressively increase in size the further the sub-contact is from the planar surface 148.

In an embodiment, a volume of conductive material for the first line 154(1) is substantially equal to a volume of conductive material for the second line 154(2). In this context, the volumes of conductive material are considered to be substantially equal if they are within 5% of each other. To accomplish this design goal, the layout designer selects the widths and lengths of the sub-lines for each of the sub-layers.

Additionally, the first and second sub-lines are positioned immediately adjacent each other without any intervening metal structure within said same dielectric layer 156. In this configuration, a first spacing distance in a direction parallel to the planar surfaces between first and second sub-lines on different sub-layers is less than a second spacing distance the direction parallel to the planar surfaces between first and second sub-lines located on different sub-layers. Indeed, this first spacing distance may be negative in that some overlap between sub-lines on different sub-layers in the vertical direction perpendicular to the planar surfaces is provided. This overlap is generally indicated at reference 168.

FIG. 10 illustrates a perspective view of the contacts 150 and the lines 154(1) and 154(2) for the configuration shown in FIG. 9 (wherein the structures relating to the gate electrode and contact 152 are omitted to simplify the illustration and ensure visibility of the structures for the contacts 150 and the lines 154(1) and 154(2)).

Although the lines 154(1) and 154(2) are shown in FIG. 10 to extend in their lengths generally parallel to each other, it will be understood that this is not a requirement. Instead, the lines 154(1) and 154(2) could extend in their lengths perpendicular to each other as shown in FIG. 11.

Each of the sub-lines may further include a barrier liner (for example, made of titanium nitride (TiN)) to protect against diffusion of the metal species used for the sub-line into the sub-layers of the dielectric material layer 156.

Conventional deposit, pattern and fill process steps may be used to produce the sub-layers and sub-lines. For example, a mask defining the location of openings for the sub-lines may be produced on top of a given sub-layer of the dielectric material layer 156. An opening is then formed in that given sub-layer using the mask and a reactive ion etch (ME) is performed through the mask. The etch should extend completely through the given sub-layer to form the opening. An atomic layer deposition (ALD) technique is then used to deposit the metal barrier liner (such as TiN) on the walls of the opening, and a metal filling process (such as thermal chemical vapor deposition (CVD)) is then used to fill the opening with the metal material of the sub-line (such as copper or aluminum). A chemical-mechanical polishing (CMP) process is then performed to remove excess metal barrier and fill material, with the CMP stopping at the top of the given sub-layer of the dielectric material layer 156. A chemical vapor deposition (CVD) process is then performed to deposit the next sub-layer of the dielectric material layer 156. The previous steps are then repeated to form the sub-line in that next sub-layer. The process may be repeated as many times as are necessary to define the thickness of the metallization layer from multiple deposited, patterned and filled sub-layers with sub-lines. For example, the metallization layer may have a thickness of 48 to 120 nm, with each sub-layer having a thickness of between 16 and 40 nm. The minimum dimension of the sub-lines is set by the minimum dimension of the lithographic process used for fabrication.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention.

However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims. 

What is claimed is:
 1. An integrated circuit, comprising: a substrate; and conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and wherein: the first interconnect structure is adjacent to the second interconnect structure; the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level; the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure; the second interconnect structure includes a first substructure at the first level and a second substructure at the second level; the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure; and the second substructure of the second interconnect structure having a length greater than a length of the second substructure of the first interconnect structure.
 2. The circuit of claim 1, wherein the second substructure of the first interconnect structure is electrically connected with the first substructure of the first interconnect structure.
 3. The circuit of claim 1, wherein the second substructure of the first interconnect structure is in physical contact with the first substructure of the first interconnect structure.
 4. The circuit of claim 1, wherein the second substructure of the second interconnect structure is electrically connected to the first substructure of the second interconnect structure.
 5. The circuit of claim 1, wherein the second substructure of the second interconnect structure is in physical contact with the first substructure of the second interconnect structure.
 6. The circuit of claim 1, wherein the second substructure of the first structure is in physical contact with the first substructure of the first interconnect structure, and wherein the second substructure of the second interconnect structure is in physical contact with the first substructure of the second interconnect structure.
 7. The circuit of claim 1, wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.
 8. The circuit of claim 7, wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the second distance.
 9. The circuit of claim 7, wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the first distance.
 10. The circuit of claim 9, wherein the third distance is greater than the second distance.
 11. An integrated circuit, comprising: a substrate; and conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and wherein: the first interconnect structure is adjacent the second interconnect structure; the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level; the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure; the second interconnect structure includes a first substructure at the first level and a second substructure at the second level; the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; and wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.
 12. The circuit of claim 11, wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the second distance.
 13. The circuit of claim 11, wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the first distance.
 14. The circuit of claim 13, wherein the third distance is greater than the second distance.
 15. The circuit of claim 11, wherein the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure, and the second substructure of the second interconnect structure has a length greater than a length of the second substructure of the first interconnect structure.
 16. An integrated circuit, comprising: a substrate; and conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and wherein: the first interconnect structure is adjacent to the second interconnect structure; the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level; the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure; the second interconnect structure includes a first substructure at the first level and a second substructure at the second level; the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure; the second substructure of the second interconnect structure having a length greater than a length of the second substructure of the first interconnect structure; and wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.
 17. The circuit of claim 17, wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the second distance.
 18. The circuit of claim 17, wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the first distance.
 19. The circuit of claim 18, wherein the third distance is greater than the second distance.
 20. The circuit of claim 16, wherein the second substructure of the first structure is in physical contact with the first substructure of the first interconnect structure, and wherein the second substructure of the second interconnect structure is in physical contact with the first substructure of the second interconnect structure. 